RXFIFORES=NO_EFFECT, FIFOEN=DISABLED, RXTRIGLVL=LEVEL_0, TXFIFORES=NO_EFFECT
FIFO Control Register. Controls UART1 FIFO usage and modes.
| FIFOEN | FIFO enable. 0 (DISABLED): Disabled. Must not be used in the application. 1 (ENABLED): Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs. |
| RXFIFORES | RX FIFO Reset. 0 (NO_EFFECT): No effect. No impact on either of UART1 FIFOs. 1 (CLEAR): Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing. |
| TXFIFORES | TX FIFO Reset. 0 (NO_EFFECT): No effect. No impact on either of UART1 FIFOs. 1 (CLEAR): Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing. |
| DMAMODE | DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| RXTRIGLVL | RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated. 0 (LEVEL_0): Level 0. Trigger level 0 (1 character or 0x01). 1 (LEVEL_1): Level 1. Trigger level 1 (4 characters or 0x04). 2 (LEVEL_2): Level 2. Trigger level 2 (8 characters or 0x08). 3 (LEVEL_3): Level 3. Trigger level 3 (14 characters or 0x0E). |
| RESERVED | Reserved, user software should not write ones to reserved bits. |